AI Based Wafer Map Analysis System

Semiconductor process manufacturing flows, used to create Integrated Circuits, take months to complete and comprise hundreds of processing steps, using a variety of complex equipment. Electrical results at end-of-line and their spatial distribution across silicon wafers  are critically  important for the timely diagnosis and resolution of in-line issues.   Automatic Wafermap Recognition System is designed to automatically categorise wafer maps by spatial distribution. Thus, enabling a timely correlation to in-line equipment and processing parameters. The classification of these patterns and their tracing to root cause is currently an engineering intensive activity that is optimised and made more consistent by the implementation of this system. Using this research, the company defines existing failure patterns and uses these to generate a model.   This model can then automatically categorise new wafer maps by these failure types and give early warnings of out-of-control events that are impacting the end-of-line performance.   Both the cost incurred by an out-of-control product and time delays in resolving issues can be minimised by using this system. Products manufactured can have different die sizes and this can lead to different patterns at end-of-line for the same root cause issue. This system standardises the maps automatically and, by employing specific algorithms,  allows one model to be used across a broad range of die sizes – ensuring patterns are consistently detected.